Random Access Memory (RAM) tends to be an integrated circuit (IC) technology in which individual dense memory storage cells, such as capacitive cells, are grouped into various two-dimensional matrices, such that the state of each memory cell may easily be read and/or altered. Very early RAMs held perhaps a few thousand bits; today RAM size has advanced roughly one-million fold: RAMs are now available with more than 1 billion bits on a single silicon die. But during the evolution of RAM technology there has been a massive skew in the difference between some RAM cycle times, in particular capacitive cell Dynamic RAM (DRAM), and the cycle times of other ICs used in a computing system, such as Central Processing Unit (CPU) and/or Input/Output Control (IOC) circuits which access the DRAMs. While DRAM performance has increased very lithe, CPU and IOC circuit speeds have increased by several powers of ten.
The performance discrepancy is in part due to reliance on a RAM architecture which has passed a point of diminishing returns. Each new generation of RAM chips uses a set of parallel paths by which address and data signals arrive at the chip, and/or by which data signals leave the chip. Any RAM interface, no matter what its design or construction, must convey address information, which at present requires slightly less than 30 bits. It must also include a data word of typically 16 or 32 bits; current interfaces present all or a major portion of these bits as separate, parallel signals, one signal per pin. Some arrangements use additional qualifying signals on other pins such that the data and address signals may share pins; this trades off pin count, i.e. the fewer pins the better, against overall interface complexity, which is increased, and latency, which is also increased, when multiple sets of information must use the same pins. Thus each increase in RAM density must either increase the pin count or add complexity and latency to the interface. Even the most powerful current RAM interface, known commonly as RAMBus®, uses a fixed set of parallel signaling lines.
Use of many parallel signal paths further demands that they be used in the nature of a “bus”, i.e. physical signal paths are used to pass signals in both directions depending on an operational phase, and many individual ICs are connected to each physical signal path. Large amounts of power are necessary to successfully drive each bus signal, relative to the power needed to drive a signal in only one direction and only from one IC to one other IC. Further, a relatively long time is needed to drive each bus signal across a lengthy physical path and register successfully on each of the many sensing circuit elements. Since there may be many such paths operating in parallel, they also occupy large amounts of physical space on the chip edge and on the printed circuit board; the bulk and power demands of this style of interface impose severe physical limits on the advance of total system memory bandwidth.
Internally the memory cells of a RAM tend to occur in two-dimensional patterns of rows and columns. For instance, to read a RAM it is necessary to select and stimulate a single row; each cell on that row then dumps its data load onto a sense line which descends a column sense line to the bottom of the array, and when all sense lines have taken a stable state the bits of that row are known. A read operation may have to immediately restore these states, if e.g. it has emptied each element in the selected row; a write operation may tend to initiate a read to clear all bits, then replace the old states with new data and perform the “restore” step.
In fact a chief obstacle impeding improvement in DRAM performance has been the relatively poor quality and large size of the random logic circuit elements on the DRAM die, which tends to use a Negative Metal Oxide Semiconductor, or NMOS, integrated circuit process. NMOS makes possible a very dense array of capacitive cells; but also produces slow, bulky logic gates.
Thus there exists a need for an improved random access memory that has considerably faster cycle times than present DRAMs.